Welcome to Ceramic Hacker
Recent blog posts
[14/12] Hardcaml MIPS and I/O
Accessing external IO devices with Hardcaml. Memory-Mapped IO vs Post-Mapped IO. Bus-driven CPU architecture, UART protocol / implementation. Project limitations and hypothetical expansions. Testing design with UART-driven calculator.
[7/7] Routing in Bonsai and Project Conclusion
Building a basic routing system in Bonsai to showcase global state and higher-order components. Project and blog series conclusion.
[6/x] Using GraphQL in Bonsai
OCaml Bonsai frontend integration with GraphQL. Building a GraphQL client and query loader component in OCaml with Bonsai.
[5/x] Understanding Bonsai
Background for understanding Bonsai: SPAs, frontend state management, algebraic effects, monads, incremental computations. Bonsai `Value` vs `Computation`, and usage of `sub` and `arr` combinators.
[4/x] Setting up Bonsai
OCaml Single Page Application frontend with Bonsai setup and basic intro. Simple component examples and Dune config.
[3/x] Building GraphQL APIs with Dream
OCaml GraphQL API tutorial and example. Live GraphiQL demo.
[2/x] Backend WebDev w/ Dream and Caqti
OCaml Backend Web Development. Dream web server using Caqti SQL bindings, concurrency through Lwt.
[13/12] Running Hardcaml on an Actual FPGA
Deploying Hardcaml on a real Arty-A7 FPGA. Displaying program output with LEDs.
[1/x] Full-Stack WebDev in OCaml Intro
OCaml Full Stack Web Development with Dream, Bonsai, and GraphQL. Project overview, blog summary, and live demo.
[12/12] MIPS Project Conclusion
Hardcaml MIPS blog conclusion. Hardcaml strengths vs weaknesses analysis, blogging reflections.
[11/x] CPU Functionality Wrap Up
Last MIPS functionality: data hazards, forwarding, stalls, jumps, and branches. Multi-branch if-else using priority muxes.
[10/x] Testing and Debugging Hardcaml
Hardcaml automated testing, ASCII waveforms. Debugging hardware with Hardcaml's interactive waveform viewer.
[9/x] Always DSL and the Control Unit
CPU control unit implementation. Using Hardcaml's Always DSL for imperative logic in Hardcaml design.
[8/x] Design Patterns, Conventions, and Testing
Hardcaml circuit design patterns and automated testing. Using custom functor to assert wire width safety.
[7/x] Registers and Stateful Design
Sequential logic, registers/pipelines, and state in Hardcaml. Using feedback wires to increment instruction fetch program counter.
[6/x] Memory in Hardcaml
Overview of Hardcaml memory primitives, different types of CPU memory. Implementing instruction and data memory with Hardcaml Multiport Memory.
[5/x] Multi Module Circuits in Hardcaml
Building multi-module circuits with Hardcaml's hierarchical interfaces.
[4/x] OCaml Setup, Hardcaml Basics, and Project Plan
Setting up OCaml and Hardcaml using Opam and Dune. Project plan, code layout, and setup for testing, code, and generating Verilog RTL from Hardcaml.
[3/x] Verilog, FPGAs, and why OCaml
Intro to hardware design, verilog pros vs cons, Vivado IDE for synthesis / implementation, OCaml for hardware, and FPGA explanation.
[2/x] A Bit on Computers, Hardware, and CPUs
Intro to digital logic, computers, gates, combinatorial/sequential circuits, the MIPS architecture, and pipelined CPUs.