Hardcaml MIPS

An article series about using a 5-stage, pipelined MIPS CPU in Hardcaml. Analysis of hardware design with OCaml, as well as Hardcaml features/ergonomics.

[3/x] Verilog, FPGAs, and why OCaml
[1/x] Hardcaml MIPS Intro: What and Why?
[14/12] Hardcaml MIPS and I/O
[13/12] Running Hardcaml on an Actual FPGA
[12/12] MIPS Project Conclusion
[11/x] CPU Functionality Wrap Up
[10/x] Testing and Debugging Hardcaml
[8/x] Design Patterns, Conventions, and Testing
[6/x] Memory in Hardcaml
[9/x] Always DSL and the Control Unit
[7/x] Registers and Stateful Design
[5/x] Multi Module Circuits in Hardcaml
[4/x] OCaml Setup, Hardcaml Basics, and Project Plan
[2/x] A Bit on Computers, Hardware, and CPUs